Semiconductor device

ABSTRACT

A semiconductor device provided with a first semiconductor chip having a first functional surface formed with a first functional element and a first rear surface, a second semiconductor chip having a second functional surface which is formed with a second functional element, the second functional surface having a region opposed to the first functional surface of the first semiconductor chip and a non-opposed region defined outside the opposed region, a connection member electrically connecting the first functional element and the second functional element, an insulation film continuously covering the non-opposed region of the second semiconductor chip and the first rear surface of the first semiconductor chip, a rewiring layer provided on a surface of the insulation film, a protective resin layer covering the rewiring layer, and an external connection terminal projecting from the rewiring layer through the protective resin layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multichip module including aplurality of semiconductor chips.

2. Description of Related Art

In recent years, there has been a demand for higher density integrationand size reduction of a semiconductor device. To this end, a multichipmodule (MCM, see Japanese Unexamined Patent Publication No. 2000-270721)and a chip scale package (CSP, see Japanese Unexamined PatentPublication No. 2002-118224) have been developed which satisfy theaforesaid demand.

FIG. 8 is a schematic sectional view illustrating the construction of aprior art semiconductor device having a multichip module structure.

The semiconductor device 81 includes a wiring board 82, a semiconductorchip 83 disposed on the wiring board 82, and a semiconductor chip 84disposed on the semiconductor chip 83. The semiconductor chips 83, 84each include a functional element 83 a, 84 a formed in one surfacethereof. The semiconductor chip 83 is bonded onto the wiring board 82with its face up, i.e., the surface of the semiconductor chip 83 formedwith the functional element 83 a faces away from the wiring board 82.The semiconductor chip 84 is bonded onto the semiconductor chip 83 withits face up, i.e., the surface of the semiconductor chip 84 formed withthe functional element 84 a faces away from the semiconductor chip 83.An interlevel insulating material 86 is interposed between thesemiconductor chips 83 and 84.

The semiconductor chip 83 is greater in size than the semiconductor chip84 as seen perpendicularly to the surfaces formed with the functionalelements 83 a, 84 a, so that the surface of the semiconductor chip 83 onwhich the semiconductor chip 84 is bonded has a peripheral area notopposed to the semiconductor chip 84. Electrode pads 83 b connected tothe functional element 83 a are provided on the peripheral area of thesemiconductor chip 83. Electrode pads 84 b connected to the functionalelement 84 a are provided on a peripheral area of the surface of thesemiconductor chip 84 formed with the functional element 84 a.

The wiring board 82 is greater in size than the semiconductor chip 83 asseen perpendicularly to the wiring board 82, so that the surface of thewiring board 82 on which the semiconductor chip 83 is bonded has aperipheral area not opposed to the semiconductor chip 83. Electrode padsnot shown are provided on the peripheral area of the wiring board 82,and connected to the electrode pads 83 b, 84 b via bonding wires 87, 88,respectively.

The semiconductor chips 83, 84 and the bonding wires 87, 88 are sealedin a mold resin 89.

Metal balls 85 serving as external connection members are provided on asurface of the wiring board 82 opposite from the surface on which thesemiconductor chip 83 is bonded. Electrode pads (not shown) of thewiring board 82 are rewired in and on the wiring board 82 andrespectively connected to the metal balls 85.

The semiconductor device 81 is connected to a second wiring board viathe metal balls 85.

FIG. 9 is a schematic sectional view illustrating the construction of aprior art semiconductor device having a chip scale package structure.

The semiconductor device 91 includes a semiconductor chip 92. Thesemiconductor chip 92 includes a functional element 92 a formed in onesurface thereof, and an insulation film 93 covering the functionalelement 92 a. The insulation film 93 has openings formed inpredetermined portions thereof.

Rewiring layers 94 each having a predetermined pattern are provided onthe insulation film 93. The rewiring layers 94 are connected to thefunctional element 92 a through the openings of the insulation film 93.Columnar external connection terminals 95 project from predeterminedportions of the rewiring layers 94, and metal balls 96 serving asexternal connection members are respectively bonded onto distal ends ofthe external connection terminals 95.

The insulation film 93 and the rewiring layers 94 on the surface of thesemiconductor chip 92 formed with the functional element 92 a arecovered with a protective rein layer 97. The external connectionterminals 95 each extend through the protective resin layer 97. Sidesurfaces of the semiconductor chip 92 are flush with side surfaces ofthe protective resin layer 97. With the provision of the protectiveresin layer 97, the semiconductor device 91 has a generally rectangularprism outer shape. Therefore, the semiconductor device 91 hassubstantially the same size as the semiconductor chip 92 as seenperpendicularly to the semiconductor chip 92.

The semiconductor device 91 is connected to a wiring board via the metalballs 96.

In the semiconductor device 81 of FIG. 8, however, the wiring board 82should have a greater size than the semiconductor chip 83 to provide anarea for the connection with the bonding wires 87, 88. Therefore, thesemiconductor device 81 (package) is greater in size than thesemiconductor chips 83, 84, particularly, as measured parallel to thewiring board 82. Accordingly, the semiconductor device 81 requires agreater mounting area on the second wiring board.

Where a lead frame is used instead of the wiring board 82 (see, forexample, Japanese Unexamined Patent Publication No. 2002-9223), asimilar problem occurs.

On the other hand, the semiconductor device 91 of FIG. 9 includes nowiring board. With this construction, it is impossible to incorporate aplurality of chips (semiconductor chips 92) in the semiconductor device.In order to mount a plurality of semiconductor chips 92 on a wiringboard, a plurality of such semiconductor devices 91 should be arrangedlaterally on the wiring board, requiring a greater mounting area. Inaddition, the semiconductor chips 92 are connected to one another viathe wiring board, so that the total wiring length is increased. Thismakes it difficult to increase the signal processing speed of theoverall system.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a semiconductordevice of a multichip module structure which has substantially the samesize as chips incorporated therein.

It is another object of the present invention to provide a semiconductordevice of a multichip module structure which has a reduced wiringlength.

A semiconductor device according to a first aspect of the presentinvention comprises a first semiconductor chip having a first functionalsurface formed with a first functional element and a first rear surfacewhich is opposite from the first functional surface, a secondsemiconductor chip having a second functional surface which is formedwith a second functional element, the second functional surface having aregion opposed to the first functional surface of the firstsemiconductor chip and and a non-opposed region defined outside theopposed region, a connection member provided between the firstfunctional surface and the second functional surface and electricallyconnecting the first functional element and the second functionalelement, an insulation film continuously covering the non-opposed regionof the second semiconductor chip and the first rear surface of the firstsemiconductor chip, a rewiring layer provided on a surface of theinsulation film and electrically connected to the second functionalelement, a protective resin layer covering the rewiring layer, and anexternal connection terminal projecting from the rewiring layer throughthe protective resin layer.

The inventive semiconductor device is a multichip module including thefirst and second semiconductor chips. According to the presentinvention, the first functional element of the first semiconductor chipand the second functional element of the second semiconductor chip areelectrically connected to each other with the first functional surfaceand the second functional surface opposed to each other. Therefore, thelength of a wiring between the semiconductor chips can be drasticallyreduced as compared with a case where a plurality of single-chipsemiconductor devices are mounted on a wiring board. Thus, the inventivesemiconductor device is capable of operating at a higher speed.

The connection member which electrically connects the first functionalelement of the first semiconductor chip and the second functionalelement of the second semiconductor chip may comprise, for example,bumps (projection electrodes) respectively provided on the first andsecond functional surfaces and bonded to each other. Alternatively, theconnection member may comprise a bump provided on one of the first andsecond functional surfaces and bonded to the other functional surface.With the connection member, it is also possible to achieve mechanicalconnection between the first semiconductor chip and the secondsemiconductor chip.

In the semiconductor device, the first semiconductor chip may comprise aplurality of first semiconductor chips. In this case, the firstsemiconductor chips are each electrically connected to the secondsemiconductor chip with the first functional surface thereof opposed tothe second functional surface. In this case, the length of wiringsbetween the first functional elements of the first semiconductor chipsand second functional elements of the second semiconductor chip and thelength of wirings between the first functional elements of the firstsemiconductor chips via the second semiconductor chip are equivalent tothe length of wirings between the second functional elements of thesecond semiconductor chip. Therefore, the semiconductor device iscapable of operating at a higher speed.

The semiconductor device can be mounted on a wiring board via theexternal connection terminal. An external connection member such as ametal ball may be bonded to a distal end of the external connectionterminal. In this case, the semiconductor device can be mounted on thewiring board via the external connection member.

The first semiconductor chip is preferably dimensioned and positioned soas to be substantially completely confined within the area of the secondsemiconductor chip as seen perpendicularly to the second functionalsurface. In this case, an area required for mounting the semiconductordevice on the wiring board is substantially equivalent to the area ofthe semiconductor chip as seen perpendicular to the second functionalsurface. That is, the semiconductor device permits higher densityintegration of semiconductor chips per unit mounting area.

The insulation film is continuously provided over the non-opposed regionof the second semiconductor chip and the first rear surface of the firstsemiconductor chip, so that the rewiring layer can be formed in anydesired wiring pattern in any desired position on the surface of theinsulation film. Therefore, the number of external connection terminalsto be provided on the rewiring layer can be increased, as long asreduction of the size and pitch of the external connection terminalsdoes not adversely influence the mounting accuracy.

The insulation film may also cover side surfaces of the semiconductorchips.

The surface of the insulation film provided with the rewiring layer mayinclude a substantially flat surface extending over the non-opposedregion and the first semiconductor chip.

With this arrangement, the external connection terminals each projectfrom the rewiring layer provided on the flat surface of the insulationfilm. Since the semiconductor device is mounted on the wiring board withdistal ends of the external connection terminals connected to the wiringboard, the distal ends of the respective external connection terminalsare present in substantially the same plane. Therefore, externalconnection terminals provided on the non-opposed region and externalconnection terminals provided on the first semiconductor chip in theinventive semiconductor device have substantially the same small height.

The external connection terminals may be formed, for example, by forminga protective resin layer having openings in external connection terminalformation regions and then depositing a metal material in the openingsby plating. Therefore, the formation of the external connectionterminals having substantially the same small height can be achieved ina shorter time. Thus, the formation of the external connection terminalsof the inventive semiconductor device is facilitated.

At least a part of the rewiring layer may be electrically connected tothe first rear surface of the first semiconductor chip.

With this arrangement, the first rear surface of the first semiconductorchip is maintained at a predetermined potential via the rewiring layerelectrically connected to the first rear surface of the firstsemiconductor chip. Therefore, the potential of the first rear surfaceof the first semiconductor chip is stabilized. Thus, the characteristicsof the first semiconductor chip can be stabilized.

The rewiring layer electrically connected to the first rear surface ofthe first semiconductor chip may be grounded.

The inventive semiconductor device may further comprise a heat-sinkterminal projecting from the first rear surface of the firstsemiconductor chip through the protective resin layer.

With this arrangement, heat generated by the first semiconductor chipcan be dissipated out of the semiconductor device via the heat-sinkterminal through a short distance. For improvement of the heatdissipation, it is preferred to provide a plurality of heat-sinkterminals.

The heat-sink terminal may be composed of, for example, the samematerial as the external connection terminals. In this case, theheat-sink terminal and the external connection terminals may besimultaneously formed by electrolytic plating.

An electrically conductive film may be provided between the first rearsurface of the first semiconductor chip and the heat-sink terminal. Inthis case, the electrically conductive film and the rewiring layer maybe composed of the same material. In this case, the rewiring layer andthe electrically conductive film may be simultaneously formed.

The inventive semiconductor device may further comprise a diffusionprevention film of an electrically conductive material provided betweenthe first rear surface of the first semiconductor chip and theinsulation film and between the first rear surface and the heat-sinkterminal.

With this arrangement, the diffusion prevention film is provided betweenthe first rear surface of the first semiconductor chip and theinsulation film, i.e., below the insulation film. In a productionprocess for the semiconductor device, the diffusion prevention film isfirst formed on the first rear surface of the first semiconductor chip,and the insulation film is formed as having an opening at apredetermined position on the diffusion prevention film. Then, theheat-sink terminal is formed so as to be connected to the first rearsurface of the first semiconductor chip through the opening.

Where the insulation film is formed on the first rear surface of thefirst semiconductor chip without the formation of the diffusionprevention film and then the diffusion prevention film is formed on aportion of the first rear surface of the first semiconductor chipexposed in the opening of the insulation film, it may be impossible tocompletely cover the exposed portion of the first rear surface of thefirst semiconductor chip with the diffusion prevention film thus formed.In this case, the diffusion prevention film is liable to have holes inthe vicinity of the interior surface of the opening of the insulationfilm and, if the metal heat-sink terminal is formed on the diffusionprevention film, metal atoms of the heat-sink terminal will diffuse intothe first semiconductor chip through the holes of the diffusionprevention film. In this case, the characteristics of the firstsemiconductor chip will vary.

In the production process for the inventive semiconductor device, on thecontrary, the diffusion prevention film can be formed on the first rearsurface (preferably on the entire first rear surface) of the firstsemiconductor chip before the formation of the insulation film.Therefore, the diffusion prevention film thus formed is free from theholes, so that the first rear surface of the first semiconductor chipcan be completely covered with the diffusion prevention film. Thus, thediffusion of the metal atoms of the heat-sink terminal into the firstsemiconductor chip and hence the variation in the characteristics of thefirst semiconductor chip can be suppressed.

The diffusion prevention film may be composed of, for example, a knownUBM (under-bump metal) material or the like.

An electrically conductive film composed of the same material as therewiring layer may be provided between the diffusion prevention filmprovided on the first rear surface of the first semiconductor chip andthe heat-sink terminal. In this case, the provision of the diffusionprevention film suppresses (prevents) the diffusion of atoms (metalatoms) of the electrically conductive film into the first semiconductorchip.

The inventive semiconductor device may further comprise a diffusionprevention film of an electrically conductive material provided betweenthe first rear surface of the first semiconductor chip and theinsulation film and between the first rear surface and the rewiringlayer.

With this arrangement, the diffusion prevention film is provided betweenthe first rear surface of the first semiconductor chip and theinsulation film, i.e., below the insulation film. In the productionprocess for the semiconductor device, the diffusion prevention film isformed on the first rear surface of the first semiconductor chip, andthe insulation film is formed as having an opening at a predeterminedposition on the diffusion prevention film. Then, the rewiring layer isformed so as to be connected to the first rear surface of the firstsemiconductor chip through the opening.

Since the formation of the diffusion prevention film precedes theformation of the insulation film, the diffusion prevention film is freefrom holes. Therefore, the first rear surface of the first semiconductorchip can be completely covered with the diffusion prevention film. Thus,the diffusion of atoms (metal atoms) of the rewiring layer and hence thevariation in the characteristics of the first semiconductor chip can besuppressed.

The diffusion prevention film may be composed of, for example, a knownUBM material or the like.

The inventive semiconductor device may further comprise a rear surfaceprotective film provided on a second rear surface of the secondsemiconductor chip which is opposite from the second functional surface.

With this arrangement, the second rear surface of the secondsemiconductor chip can be protected mechanically and electrically by therear surface protective film.

Where the rear surface protective film is not provided, the secondsemiconductor chip is liable to be warped due to stress imbalanceoccurring along the thickness of the second semiconductor chip by theprovision of the insulation film and the protective resin layer on oneof the surfaces (functional surface) of the second semiconductor chip.In the inventive semiconductor device, however, the rear surfaceprotective film is provided on the other surface (rear surface) of thesecond semiconductor chip, so that stresses exerted on the secondsemiconductor chip can be properly balanced along the thickness of thesecond semiconductor chip. Thus, the warp of the second semiconductorchip can be mitigated (prevented).

The rear surface protective film may be composed of, for example, aresin.

The inventive semiconductor device may further comprise a via-conductorprojecting from the non-opposed region of the second semiconductor chipthrough the insulation film and electrically connecting the secondfunctional element and the rewiring layer.

With this arrangement, the via-conductor can be formed as projectingfrom the non-opposed region of the second semiconductor chip prior tothe formation of the insulation film when the semiconductor device isproduced. Thereafter, the insulation film is formed so that thevia-conductor extends through the insulation film. Then, the rewiringlayer is formed so as to be electrically connected to the via-conductor.

Where no via-conductor is to be provided, it is necessary to form theinsulation film and then form an opening in the insulation film for theprovision of the rewiring layer. According to the present invention, onthe contrary, the opening formation step can be obviated.

A semiconductor device according to a second aspect of the presentinvention comprises a semiconductor chip having a functional elementformed in one surface thereof, an insulation film covering a rearsurface of the semiconductor chip which is opposite from the surfaceformed with the functional element, an electrically conductive memberelectrically connected to the rear surface of the semiconductor chipthrough an opening formed in the insulation film, and a diffusionprevention film provided between the rear surface of the semiconductorchip and the insulation film and between the rear surface and theelectrically conductive member.

According to the present invention, the rear surface of thesemiconductor chip can be maintained at a predetermined potential viathe electrically conductive member. Thus, the potential of the rearsurface of the semiconductor chip can be stabilized, thereby stabilizingthe characteristics of the semiconductor chip. The electricallyconductive member may be, for example, grounded.

The diffusion prevention film is provided between the rear surface ofthe semiconductor chip and the insulation film, i.e., below theinsulation film. In a production process for the semiconductor device,the insulation film is first formed as having an opening at apredetermined position on the diffusion prevention film formed on therear surface of the semiconductor chip, and then the electricallyconductive member is formed so as to be electrically connected to therear surface of the semiconductor chip through the opening.

Since the formation of the diffusion prevention film precedes theformation of the insulation film, the rear surface of the semiconductorchip can be completely covered with the diffusion prevention film thusformed. The provision of the diffusion prevention film suppresses thediffusion of atoms (metal atoms) of the electrically conductive materialinto the semiconductor chip and hence the variation in thecharacteristics of the semiconductor chip.

The semiconductor device which includes the semiconductor chip havingthe functional element provided on one surface thereof can be producedby a semiconductor device production process which comprises the stepsof: forming a diffusion prevention film of an electrically conductivematerial on a rear surface (preferably on the entire rear surface) ofthe semiconductor chip which is opposite from the surface formed withthe functional element; forming an insulation film on the diffusionprevention film, the insulation film having an opening through which apart of the diffusion prevention film is exposed; and forming anelectrically conductive member electrically connected to the rearsurface of the semiconductor chip through the opening of the insulationfilm.

The foregoing and other objects, features and effects of the presentinvention will become more apparent from the following description ofthe preferred embodiments with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic sectional view illustrating the construction of asemiconductor device according to a first embodiment of the presentinvention;

FIG. 2 is a schematic sectional view illustrating the construction of asemiconductor device according to a second embodiment of the presentinvention;

FIG. 3 is a schematic sectional view illustrating the construction of asemiconductor device according to a third embodiment of the presentinvention;

FIG. 4 is a schematic sectional view illustrating the construction of asemiconductor device according to a fourth embodiment of the presentinvention;

FIG. 5 is a schematic sectional view illustrating, on an enlarged scale,a junction between a rear surface of a first semiconductor chip and aheat-sink terminal in the semiconductor device shown in FIG. 4;

FIG. 6 is a schematic sectional view illustrating the construction of asemiconductor device according to a fifth embodiment of the presentinvention;

FIG. 7 is a schematic sectional view illustrating the construction of asemiconductor device according to a sixth embodiment of the presentinvention;

FIG. 8 is a schematic sectional view illustrating the construction of aprior art semiconductor device having a multichip module structure; and

FIG. 9 is a schematic sectional view illustrating the construction of aprior art semiconductor device having a chip scale package structure.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a schematic sectional view illustrating the construction of asemiconductor device according to a first embodiment of the presentinvention.

The semiconductor device 1 is a so-called chip scale package (CSP) of amultichip module type which includes first and second semiconductorchips 2, 3.

The first semiconductor chip 3 has a first functional surface 3F formedwith a first functional element 3 a and a rear surface 3R opposite fromthe first functional surface 3F. Further, the second semiconductor chip2 has a second functional surface 2F formed with a second functionalelement 2 a. For example, the first functional element 3 a and thesecond functional element 2 a may each be a transistor. The firstsemiconductor chip 3 and the second semiconductor chip 2 are disposed inspaced parallel relation with the first functional surface 3F and thesecond functional surface 2F opposed to each other.

The first functional element 3 a and the second functional element 2 aare electrically connected to each other via connection members 4disposed between the first semiconductor chip 3 (first functionalsurface 3F) and the second semiconductor chip 2 (second functionalsurface 2F). The connection members 4 may each be such that a bump(projection electrode) provided at a predetermine position on the firstfunctional surface 3F and a bump provided at a predetermined position onthe second functional surface 2F are connected to each other.Alternatively, the connection members 4 may each be such that a bumpprovided on one of the first and second functional surfaces 3F, 2F isconnected to the other functional surface 2F, 3F. Mechanical connectionbetween the first semiconductor chip 3 and the second semiconductor chip2 is also achieved by the connection members 4.

An interlevel seal (under-fill) layer 5 is provided as filling a spacebetween the first semiconductor chip 3 and the second semiconductor chip2.

The first semiconductor chip 3 is smaller in size than the secondsemiconductor chip 2 as seen perpendicularly to the second functionalsurface 2F, and is completely confined within the area of the secondsemiconductor chip 2. The first semiconductor chip 3 is disposedgenerally centrally of the second functional surface 2F of the secondsemiconductor chip 2. Therefore, the second functional surface 2F has aperipheral area (hereinafter referred to as “non-opposed region”) 7which is not opposed to the first semiconductor chip 3.

The second functional element 2 a is provided over the non-opposedregion 7 and an opposed region of the second functional surface 2F towhich the first semiconductor chip 3 is opposed.

An insulation film 8 is continuously provided as covering a part of thenon-opposed region 7 formed with the second functional element 2 a, sidesurfaces of the interlevel seal layer 5 and the rear surface 3R and sidesurfaces of the first semiconductor chip 3. The insulation film 8 iscomposed of, for example, a polyimide, a polybenzoxazole, an epoxy,silicon oxide or silicon nitride. The insulation film 8 has a generallyuniform thickness.

Rewiring layers 9 each having a predetermined pattern are provided onthe insulation film 8. The rewiring layers 9 are present on theinsulation film 8 on the non-opposed region 7 and the firstsemiconductor chip 3.

The insulation film 8 has openings 8 a provided therein on thenon-opposed region 7, and electrode pads (not shown) provided onpredetermined areas of the second functional element 2 a are exposed inthe openings 8 a. The rewiring layers 9 are electrically connected tothe electrode pads on the second functional element 2 a through theopenings 8 a of the insulation film 8.

The electrode pads on the second functional element 2 a and the rewiringlayers 9 may be composed of different materials. For example, theelectrode pads may be composed of aluminum (Al), and the rewiring layers9 may be composed of copper (Cu). In this case, UBM (under-bump metal)layers (not shown) are preferably provided between the electrode pads onthe second functional element 2 a and the rewiring layers 9.Alternatively, the electrode pads on the second functional element 2 aand the rewiring layers 9 may be composed of the same material.

A protective resin layer 12 is provided on the side of the secondfunctional surface 2F of the second semiconductor chip 2 as covering theinsulation film 8 and the rewiring layers 9. Side surfaces of the secondsemiconductor chip 2 are flush with side surfaces of the protectiveresin layer 12. With the provision of the protective rein layer 12, thesemiconductor device 1 has a generally rectangular prism outer shape.

External connection metal terminals 10 project from predeterminedpositions of the rewiring layers 9 provided on the non-opposed region 7and the rewiring layers 9 provided on the first semiconductor chip 3through the protective resin layer 12. The external connection terminals10 are composed of a metal (e.g., copper, nickel (Ni), gold (Au) ortungsten (W)), and each have a columnar outer shape (e.g., a cylindricalshape or a rectangular prism shape).

Distal ends of the external connection terminals 10 are present insubstantially the same plane. Connection interfaces between the externalconnection terminals 10 and metal balls 11 are present in substantiallythe same plane as a surface of the protective resin layer 12. That is,the external connection terminals 10 projecting from the rewiring layers9 on the non-opposed region 7 each have a greater height than theexternal connection terminals 10 projecting from the rewiring layers 9on the first semiconductor chip 3.

The metal balls 11 serving as external connection members arerespectively bonded onto the distal ends of the external connectionterminals 10. The semiconductor device 1 can be mounted on a wiringboard via the metal balls 11.

As described above, the semiconductor device 1 has substantially thesame size as the second semiconductor chip 2 (which is the largest chipin the semiconductor device 1) as seen perpendicularly to the secondfunctional surface 2F, so that the semiconductor device 1 requires asmaller mounting area on the wiring board. That is, the semiconductordevice 1 permits higher density integration of first and secondsemiconductor chips 3, 2 per unit mounting area.

The first functional element 3 a and the second functional element 2 aare connected in face-to-face relation with the first and secondfunctional surfaces 3F, 2F opposed to each other. Therefore, the lengthof wirings between the first functional element 3 a and the secondfunctional element 2 a of the respective chips (first and secondsemiconductor chips 3, 2) in the semiconductor device 1 is reduced ascompared with a case where a plurality of prior art semiconductordevices 91 (see FIG. 9) are mounted on the wiring board or a prior artsemiconductor device 81 (see FIG. 8) is mounted on the wiring board.Thus, the semiconductor device 1 is capable of operating at a higherspeed.

The rewiring layers 9 may each be formed in any desired wiring patternin any desired position on the surface of the insulation film 8.Therefore, the number of the external connection terminals 10 providedon the rewiring layers 9 can be increased, as long as reduction of thesize and pitch of the external connection terminals 10 does notadversely influence the mounting accuracy.

The semiconductor device 1 can be produced, for example, on a waferbasis. More specifically, the production of the semiconductor device 1can be achieved by preparing a large substrate (e.g., a semiconductorwafer) having a plurality of second semiconductor chip regions denselyarranged therein, simultaneously connecting first semiconductor chips 3to the respective second semiconductor chip regions of the substrate,filling an interlevel sealing agent 5 in spaces between the secondsemiconductor chip regions of the substrate and the first semiconductorchips 3, forming an insulation film 8, forming rewiring layers 9,forming a protective resin layer 12, forming external connectionterminals 10, bonding metal balls 11 to the respective externalconnection terminals 10, and dicing the substrate together with theprotective resin layer 12 along boundaries between the secondsemiconductor chip regions into a plurality of semiconductor devices 1.

The formation of the insulation film 8 may be achieved, for example, byapplying a low viscosity resin on non-opposed regions 7 of the substrate(second semiconductor chip regions) and side surfaces and rear surfaces3R of the first semiconductor chips 3 by spin coating after connectingthe first semiconductor chips 3 to the substrate and filling the spaceswith the interlevel sealing agent 5, and then curing the resin. Theinsulation film 8 may be formed from a photosensitive resin. In thiscase, the insulation film 8 is formed as having a predetermined patternwith openings 8 a by applying a liquid photosensitive resin over asurface of the substrate connected to the first semiconductor chips 3with the interlevel sealing agent 5 filled in the spaces between thesubstrate and the first semiconductor chips 3, and exposing anddeveloping the photosensitive resin.

The formation of the external connection terminals 10 may be achieved,for example, by forming the protective resin layer 12 over a surface ofthe substrate formed with the insulation film 8, forming openings inexternal connection terminal formation regions of the protective resinlayer 12, forming a seed layer over a surface of the substrate formedwith the protective resin layer 12 (including interior surfaces of theopenings), and then depositing a metal material on the seed layer tofill the openings with the metal material by electrolytic plating.

FIG. 2 is a schematic sectional view illustrating the construction of asemiconductor device according to a second embodiment of the presentinvention. In FIG. 2, components corresponding to those shown in FIG. 1are denoted by the same reference characters as in FIG. 1, and noexplanation will be given thereto.

The semiconductor device 21 includes an insulation film 22 instead ofthe insulation film 8 shown in FIG. 1. The insulation film 22 isprovided over the non-opposed region 7 and the first semiconductor chip3, and has a greater thickness on the non-opposed region 7 than on thefirst-semiconductor chip 3. Thus, the surface of the insulation film 22formed with the rewiring layers 9 is substantially flat over thenon-opposed region 7 and the first semiconductor chip 3. Therefore, theexternal connection terminals 10 have substantially the same height.

The rewiring layers 9 are connected to the electrode pads on the secondfunctional element 2 a through openings 22 a formed in the insulationfilm 22. The rewiring layers 9 partly extend along interior surfaces ofthe openings 22 a, and the insides of the openings 22 a are filled withthe protective resin layer 12.

Where the external connection terminals 10 are formed as having asmaller height, the protective resin layer 12 has shallow openings inthe external connection terminal formation regions thereof. Therefore,the deposition of the metal material in the openings requires a shorterperiod of time for the formation of the external connection terminals10.

Since the external connection terminals 10 to be formed havesubstantially the same height, the openings formed in the protectiveresin layer 12 are filled up with the metal material at substantiallythe same time, for example, by the plating described above. Therefore,the plating can be terminated without over-deposition of the metalmaterial in the openings. This obviates the need for removing a part ofthe metal material deposited over the openings on the protective resinlayer 12 or reduces the time required for the removal of theover-deposited metal material. Thus, the external connection terminals10 of the semiconductor device 21 can be easily formed.

FIG. 3 is a schematic sectional view illustrating the construction of asemiconductor device according to a third embodiment of the presentinvention. In FIG. 3, components corresponding to those shown in FIGS. 1and 2 are denoted by the same reference characters as in FIGS. 1 and 2,and no explanation will be given thereto.

The semiconductor device 31 includes a rewiring layer 32A connected tothe second functional element 2 a through an opening 22 a formed in theinsulation film 22 and a rewiring layer 32B connected to the secondfunctional element 2 a through another opening 22 a formed in theinsulation film 22 and to the rear surface 3R of the first semiconductorchip 3.

A center portion of the rear surface 3R of the first semiconductor chip3 is not covered with the insulation film 8, but covered with therewiring layer 32B.

Some of the metal balls 11 are connected to the rewiring layer 32A orthe rewiring layer 32B via external connection terminals 10 not shown inthe section in FIG. 3.

With the aforesaid arrangement, some of the external connectionterminals 10 are electrically connected to the rear surface 3R of thefirst semiconductor chip 3 via the rewiring layer 32B. The rear surface3R of the first semiconductor chip 3 can be maintained at apredetermined potential via the external connection terminals 10. Thus,the potential of the rear surface 3R of the first semiconductor chip 3can be fixed, thereby stabilizing the operation characteristics of thefirst semiconductor chip 3.

The external connection terminals 10 electrically connected to the rearsurface 3R of the first semiconductor chip 3 via the rewiring layer 32Bmay serve as grounding terminals. In this case, the rear surface 3R ofthe first semiconductor chip 3 can be grounded with its potential beingfixed.

FIG. 4 is a schematic sectional view illustrating the construction of asemiconductor device according to a fourth embodiment of the presentinvention. In FIG. 4, components corresponding to those shown in FIGS. 1to 3 are denoted by the same reference characters as in FIGS. 1 to 3,and no explanation will be given thereto.

In the semiconductor device 41, the rear surface 3R of the firstsemiconductor chip 3 is mostly covered with the insulation film 22. Aportion of the insulation film 22 covering the first semiconductor chip3 has openings each having a slightly smaller width than the externalconnection terminals 10. External connection terminals (hereinafterreferred to as “heat-sink terminals”) 42 for dissipating heat and fixingthe potential of the rear surface 3R of the first semiconductor chip 3are connected to the rear surface 3R of the first semiconductor chip 3through the openings. The heat-sink terminals 42 each have the same sizeand shape as the external connection terminals 10. The heat-sinkterminals 42 are composed of the same material (metal) as the externalconnection terminals 10. Metal balls 11 are respectively bonded todistal ends of the heat-sink terminals 42.

Electrically conductive films 44 composed of the same material asrewiring layers 32A and each having substantially the same thickness asthe rewiring layers 32A are provided between the rear surface 3R of thefirst semiconductor chip 3 and the heat-sink terminals 42.

The heat-sink terminals 42 may serve as, for example, groundingterminals. By grounding the rear surface 3R of the first semiconductorchip 3 via the heat-sink terminals 42, the potential of the rear surface3R of the first semiconductor chip 3 is fixed and, hence, the operationcharacteristics of the first semiconductor chip 3 are stabilized.

In the semiconductor device 31 according to the third embodiment (seeFIG. 3), the rewiring layer 32B connected to the rear surface 3R of thefirst semiconductor chip 3 extend over the non-opposed region 7, and theexternal connection terminal 10 is bonded to the extension (the portionon the non-opposed region 7) of the rewiring layer 32B. In thesemiconductor device 41 according to the fourth embodiment, on thecontrary, the heat-sink terminals 42 are provided in adjacent relationon the rear surface 3R of the first semiconductor chip 3 with theintervention of the electrically conductive films 44. Therefore, heatgenerated by the first semiconductor chip 3 in the semiconductor device41 can be efficiently dissipated out of the semiconductor device 41 viathe heat-sink terminals 42 through a shorter distance.

A single heat-sink terminal 42 and an associated metal ball 11 may beconnected to the rear surface 3R of the first semiconductor chip 3. Evenin this case, it is possible to fix the potential of the rear surface 3Rof the first semiconductor chip 3 (by grounding the rear surface 3R ofthe first semiconductor chip 3) and to dissipate the heat generated bythe first semiconductor chip 3. However, where the plurality ofheat-sink terminals 42 and the associated metal balls 11 are provided onthe rear surface 3R of the first semiconductor chip 3 as shown in FIG.4, the heat generated by the first semiconductor chip 3 can be moreefficiently dissipated.

FIG. 5 is a schematic sectional view illustrating, on an enlarged scale,a junction between the rear surface 3R of the first semiconductor chip 3and the heat-sink terminal 42.

A diffusion prevention film 45 of an electrically conductive material isprovided over the rear surface 3R of the first semiconductor chip 3. Thediffusion prevention film 45 is disposed between the rear surface 3R ofthe first semiconductor chip 3 and the insulation film 22 and betweenthe rear surface 3R of the first semiconductor chip 3 and the heat-sinkterminals 42 (electrically conductive films 44). The diffusionprevention film 45 may also cover side surfaces of the firstsemiconductor chip 3.

The diffusion prevention film 45 is composed of a material which canprevent (suppress) diffusion of metal atoms of the heat-sink terminals42 and the electrically conductive films 44 into the first semiconductorchip 3, for example, a known UBM (under-bump metal) material such astitanium (Ti), titanium tungsten (TiW), nickel, titanium nitride (TiN)or tantalum nitride (TaN)).

For production of the semiconductor device 41, first semiconductor chips3 are connected to a substrate having a plurality of secondsemiconductor chip regions densely arranged therein in the same manneras for the production of the semiconductor device 1 of the firstembodiment. Then, a diffusion prevention film 45 is formed over asurface of the substrate to which the first semiconductor chips 3 areconnected, and a portion of the diffusion prevention film 45 presentoutside rear surfaces 3R (and side surfaces) of the first semiconductorchips 3 is removed.

Thereafter, an insulation film 22 is formed as having predeterminedopenings 22 b (see FIG. 5) on the resulting substrate, and anelectrically conductive film 44 is formed in a predetermined patternover the insulation film 22 and portions of the rear surfaces 3R of thefirst semiconductor chips 3 (diffusion prevention film 45) exposed inthe openings 22 b. Thus, semiconductor devices 41 each having aconstruction shown in FIGS. 4 and 5 are produced.

If the diffusion prevention film 45 is formed not before the formationof the insulation film 22 but after the formation of the insulation film22, portions of the rear surface 3R of the first semiconductor chip 3adjacent to the interior surfaces of the openings 22 b formed in theinsulation film 22 cannot be completely covered with the diffusionprevention film 45, and the diffusion prevention film 45 is liable tohave holes.

Before the formation of the insulation film 22, on the other hand, therear surface 3R of the first semiconductor chip 3 is flat, so that thediffusion prevention film 45 can be formed on the rear surface 3R ascompletely covering the rear surface 3R without formation of the holes.Thus, the diffusion prevention film 45 can prevent (suppress) thediffusion of the metal atoms of the heat-sink terminals 42 and theelectrically conductive film 44 into the first semiconductor chip 3.

FIG. 6 is a schematic sectional view illustrating the construction of asemiconductor device according to a fifth embodiment of the presentinvention. In FIG. 6, components corresponding to those shown in FIGS. 1to 4 are denoted by the same reference characters as in FIGS. 1 to 4,and no explanation will be given thereto.

In the semiconductor device 61, a rear surface protective film 62 isprovided on the rear surface 2R of the second semiconductor chip 2opposite from the second functional surface 2F. The rear surfaceprotective film 62 mechanically and electrically protects the rearsurface 2R of the second semiconductor chip 2.

Where the rear surface protective film 62 is not provided as in thesemiconductor device 21 of the second embodiment (see FIG. 2), theprovision of the insulation film 22 and the protective resin layer 12 onone surface (second functional surface 2F) of the second semiconductorchip 2 causes stress imbalance along the thickness of the secondsemiconductor chip 2, resulting in warp of the second semiconductor chip2. In the semiconductor device 61, on the contrary, the rear surfaceprotective film 62 is provided on the other surface (rear surface 2R) ofthe second semiconductor chip 2, whereby stresses exerted on the secondsemiconductor chip 2 are balanced along the thickness of the secondsemiconductor chip 2. Therefore, the warp of the second semiconductorchip 2 can be mitigated (prevented).

The rear surface protective film 62 may be composed of a resin such as apolyimide, a polyamide or an epoxy.

FIG. 7 is a schematic sectional view illustrating the construction of asemiconductor device according to a sixth embodiment of the presentinvention. In FIG. 7, components corresponding to those shown in FIGS. 1to 4 are denoted by the same reference characters as in FIGS. 1 to 4,and no explanation will be given thereto.

Via-conductors 72 are provided in the openings 22 a formed in theinsulation film 22 in the semiconductor device 71. The openings 22 a arefilled with the via-conductors 72. The second functional element 2 a ofthe second semiconductor chip 2 is electrically connected to therewiring layers 9 via the via-conductors 72.

When the semiconductor device 71 is produced, for example, thevia-conductors 72 are formed as projecting from the second functionalsurface 2F of the second semiconductor chip 2 before the formation ofthe insulation film 22. Thereafter, the insulation film 22 is formed sothat the via-conductors 72 extend through the insulation film 22. Then,the rewiring layers 9 are formed so as to be electrically connected tothe via-conductors 72.

Where a semiconductor device having no via-conductor 72, e.g., thesemiconductor device 21 of the second embodiment (see FIG. 2), isproduced, the insulation film 22 should first be formed and thenpatterned to be formed with the openings for the provision of therewiring layers 9 on the insulation film 22. In the production of thesemiconductor device 71, on the contrary, the opening formation step canbe obviated.

Different materials may be selected for the via-conductors 72 and therewiring layers 9.

While the embodiments of the present invention have thus been described,the present invention may be embodied in any other ways. For example,the inventive semiconductor device may include a plurality of firstsemiconductor chips 3. In this case, the first semiconductor chips 3 areelectrically connected to a second semiconductor chip 2 with firstfunctional surfaces 3F thereof opposed to a second functional surface 2Fof the second semiconductor chip 2. In this case, the length of wiringsbetween the first functional elements 3 a of the first semiconductorchips 3 and the second functional elements 2 a of the secondsemiconductor chip 2 and the length of wirings between the firstfunctional elements 3 a of the first semiconductor chips 3 areequivalent to the length of wirings between the second functionalelements 2 a of the second semiconductor chip 2. Therefore, thesemiconductor device is capable of operating at a higher speed.

In the semiconductor device 31 of the third embodiment (see FIG. 3), thesame diffusion prevention film as the diffusion prevention film 45 ofthe semiconductor device 41 of the fourth embodiment (see FIG. 5) may beprovided between the rear surface 3R of the first semiconductor chip 3and the insulation film 22 and between the rear surface 3R and therewiring layer 32B. In this case, diffusion of metal atoms of therewiring layer 32B into the first semiconductor chip 3 can be prevented(suppressed).

In the semiconductor device 1 of the first embodiment, the rewiringlayers 9 are partly disposed in the openings 8 a. Alternatively,via-conductors each having a smaller height than the via-conductors 72(see FIG. 7) (a height equivalent to the thickness of the insulationfilm 8 on the non-opposed region 7) may be provided (filled) in therespective openings 8 a. In this case, the formation of thevia-conductors may be achieved simultaneously with the formation of theconnection members 4 or the bumps for the connection members 4.

While the present invention has been described in detail by way of theembodiments thereof, it should be understood that the foregoingdisclosure is merely illustrative of the technical principles of thepresent invention but not limitative of the same. The spirit and scopeof the present invention are to be limited only by the appended claims.

This application corresponds to Japanese Patent Application No.2004-178756 filed with the Japanese Patent Office on Jun. 16, 2004, thedisclosure of which is incorporated herein by reference.

1. A semiconductor device comprising: a first semiconductor chip havinga first functional surface formed with a first functional element and afirst rear surface which is opposite from the first functional surface;a second semiconductor chip having a second functional surface which isformed with a second functional element, the second functional surfacehaving a region opposed to the first functional surface of the firstsemiconductor chip and and a non-opposed region defined outside theopposed region; a connection member provided between the firstfunctional surface and the second functional surface and electricallyconnecting the first functional element and the second functionalelement; an insulation film continuously covering the non-opposed regionof the second semiconductor chip and the first rear surface of the firstsemiconductor chip; a rewiring layer provided on a surface of theinsulation film and electrically connected to the second functionalelement; a protective resin layer covering the rewiring layer; and anexternal connection terminal projecting from the rewiring layer throughthe protective resin layer.
 2. A semiconductor device as set forth inclaim 1, wherein the surface of the insulation film provided with therewiring layer includes a substantially flat surface extending over thenon-opposed region and the first semiconductor chip.
 3. A semiconductordevice as set forth in claim 1, wherein at least a part of the rewiringlayer is electrically connected to the first rear surface of the firstsemiconductor chip.
 4. A semiconductor device as set forth in claim 1,further comprising a heat-sink terminal projecting from the first rearsurface of the first semiconductor chip through the protective resinlayer.
 5. A semiconductor device as % set forth in claim 4, furthercomprising a diffusion prevention film of an electrically conductivematerial provided between the first rear surface of the firstsemiconductor chip and the insulation film and between the first rearsurface and the heat-sink terminal.
 6. A semiconductor device as setforth in claim 1, further comprising a diffusion prevention film of anelectrically conductive material provided between the first rear surfaceof the first semiconductor chip and the insulation film and between thefirst rear surface and the rewiring layer.
 7. A semiconductor device asset forth in claim 1, further comprising a rear surface protective filmprovided on a second rear surface of the second semiconductor chip whichis opposite from the second functional surface.
 8. A semiconductordevice as set forth in claim 1, further comprising a via-conductorprojecting from the non-opposed region of the second semiconductor chipthrough the insulation film and electrically connecting the secondfunctional element and the rewiring layer.
 9. A semiconductor devicecomprising: a semiconductor chip having a functional element formed inone surface thereof; an insulation film covering a rear surface of thesemiconductor chip which is opposite from the surface formed with thefunctional element; an electrically conductive member electricallyconnected to the rear surface of the semiconductor chip through anopening formed in the insulation film; and a diffusion prevention filmprovided between the rear surface of the semiconductor chip and theinsulation film and between the rear surface and the electricallyconductive member.